What you’ll learn
The student will use knowledge of verilog to design an actual hands-on project using verilog.
The student will also learn how to translate design speicfication for actual fpga verilog project example how to allocate input / output ports
The student will learn how to break down complex designs into modules and sub modules before initial designs
The student will learn the initial steps required for every FPGA development, including allocating designing setting up modules and breaking down sub modules.
Requirements
basic syntax of verilog , system verilog or VHDL but not compulsory
Description
In this course, I will guide you through designing an actual project on FPGA using system verilog. I will you to the free software i use for analysis , synthesis, RTL simulation and verification. We start by learning how to translate design specification which will enable you to select Input output ports. Then you will learn how to break down the design into modules and how to further break down the modules into sub modules. I will be using Logism, a free software to explain the physical view of the design while we use quartus software for the actual design. Both logism and quartus are all free available software for download. At the end of the course, you will get an hands-on assignment that will further strengthen your knowledge of FPGA project designs. we will also test the final design and see how they operate in real life. simulation will be carried out on both logism and quartus. To make the course more interactive our design pick is a 5 – hand poker player chip, i will introduce the game design and model, and all steps and stages involved in the game before we put heads together to deliberate on the specification . Then we continue from scratch till we get a working poker player chip.
Overview
Section 1: Introduction
Lecture 1 1. Introducing the game design
Lecture 2 2. Introducing our design tools – logism and quartus
Lecture 3 3. The game design specification
Lecture 4 game simulation
Lecture 5 4. designing the first module – player bank
Lecture 6 5. Designing the game state machine
Lecture 7 6. Designing the card number sorting algorithm
Lecture 8 7. Card swapping algorithm module development
Lecture 9 8. Card Ranking algorithm module development
Lecture 10 9. Game state machine signal generator module design
Lecture 11 10. Control signal generator algorithm module development
Lecture 12 11. Top design of the 5 hand poker player module
Lecture 13 13. Conclusion
verilog , fpga, hardware developers and engineers
